The present invention relates generally to demodulating a suppressed carrier, quadraphase shift key (QPSK) modulated signal and more particularly, to a method and apparatus wherein the frequency of a coherent reference of a phase locked loop is dithered to derive an error signal that is compared with a source of the dithering frequency.
A widely used technique to transmit signals indicative of the binary levels of a pair of data modulating channels is quadraphase shift key (QPSK) signalling, wherein a transmitted suppressed carrier wave is represented as: EQU S(t) = .sqroot.P/2 [A sin .omega..sub.o t + B cos .omega..sub.o t](1)
wherein P = the transmitted power, .omega..sub.o = the frequency of the carrier in radians per second,
A = the binary value of one modulating channel, and
B = the binary value of the other modulating channel.
The values of A and B are associated with channels that are frequently referred to as the in-phase and quadraphase channels; the values of A and B are selectively .+-. 1 for binary values of 1 and 0, respectively. The waveform given by Equation (1) is a suppressed carrier having one of four possible phase positions, and an amplitude of .sqroot.P/2. The four phases are displaced from each other by 90.degree. and differ from axes for the in-phase and quadraphase channels by .+-.45.degree.. It is well recognized that signalling as represented by Equation (1) provides an efficient technique for transmitting digital data, both in terms of bandwidth and transmitter power. The bandwidth requirements are less than for single amplitude, frequency shift key modulation. Further, lower levels of transmitted power enable a given bit error rate (BER) to be achieved.
A problem with QPSK modulation is that it is difficult to maintain phase accuracy at the transmitting modulator. Inaccuracies in the relative phases of the signals derived from the QPSK modulator cause deviations from the ideal Equation (1) relationship, resulting in performance degradation that results in both signal amplitude loss and cross talk between the in-phase and quadraphase channels. It can be shown that the polarity of the cross talk between the channels is dependent on the modulating input data and causes a weaker or stronger effective signal to be derived for a particular bit period interval. The net result of the cross talk increases the average system BER and usually causes the BER to be dependent on a single channel, as well as both channels.
A receiver responsive to a transmitted QPSK signal demodulates the received signal into two original digital data signals, A and B. The demodulator generates a coherent reference which is compared with the input signal in a pair of quadraphase detection channels. Each channel includes a separate analog multiplier or mixer responsive to orthogonally phased components of the coherent reference and a replica of the received QPSK signal. The output signals of the mixers are applied to separate low pass filters, each having a band pass sufficiently high to enable the in-phase and quadraphase binary data to be derived as demodulated replicas of the transmitted in-phase and quadraphase data. The demodulated in-phase and quadraphase signals are typically combined to derive a control signal for a voltage controlled, variable frequency oscillator that derives the coherent reference source. The phase of the coherent reference, relative to the phase of the suppressed carrier QPSK signal supplied to the demodulator, must be very close to the original reference phase used in the modulator at the transmitter.
Various circuits have been used to control the coherent reference. However, the two most popular circuits are known as the times four/divide by four loop and the data estimation loop.
In the times four/divide by four loop, a replica of the received QPSK signal is frequency multiplied by four and mixed with the coherent reference that is also frequency multiplied by four. The mixer derives an output signal that is coupled through a low pass filter to control the frequency of the coherent reference. By frequency multiplying the coherent reference by four in a feedback loop, there is effectively a frequency division by four of the input to the multiplier from the receiver. The divide by four circuit is usually a phase locked loop with a loop bandwidth of 0.1% to 1% of the rate of the quadraphase data modulating the suppressed carrier. The narrow band loop removes most noise jitter present on the input signal and provides a stable reference for the phase detector formed by the mixer and low pass filter.
The major problem with the time four/divide by four loop is the inability of the loop to obtain adequate phase stability of the coherent reference. This problem becomes more difficult as the frequency supplied to the multiplier by the receiver increases. Also, at high data rates, the fourth harmonic of the frequency supplied to the multiplier can appear in the S or C band regions, which require difficult circuit designs.
In the data estimation loop, a Costas loop is formed by supplying the output signals of the orthogonal channel low pass filters to separate hard limiters. The output signals of the hard limiters are cross multiplied with the output signals of the low pass filters to derive estimates of the transmitted data. The estimates are compared to derive an error signal that is coupled to a loop filter, which in turn controls frequency of the coherent reference.
A major problem with the data estimation loop is that there is a possibility for the loop to lock onto relatively low spectral components that are removed in frequency from the suppressed carrier frequency of the received signal. Such relatively low amplitude spectral components are referred to as false lock components or points. The possibility of a false lock is aggravated because of data dependent noise introduced onto the signal by the modulator.
Design equations for data estimation loops have been based on small signal, error free conditions and have not, in general, represented operation for a real system. In particular, the data estimation loop has at least the following deficiencies: (1) the loop provides an error signal for the voltage controlled oscillator, but a signal to indicate lock status is not derived; (2) the design equations for the data estimation loop do not take into account the finite gain of the hard limiters; (3) the bandwidth limiting of the modulated signal is not considered; (4) transient behavior is not considered; and (5) gain and bias offsets are not considered.